The present invention relates to a memory integrated circuit, and more particularly to the so-called one-transistor type memory integrated circuit in which each memory cell is composed of one-transistor and one-capacitor.
In a memory circuit in which each memory cell is composed of a single gate transistor and a single capacitor, existence or non-existence of an electric charge stored in the capacitor is made to correspond to stored logic information. Recently, in accordance with the rapid increase of a memory capacity, individual memory cells are being reduced in size. As a result, the electrostatic capacitance of the capacitor in each memory cell has become remarkably small, and hence only a very small amount of electric charge can be stored therein. Consequently, a read-out signal from the memory cell has become very small and thus handling thereof has become difficult.
On the other hand, it has been known that if alpha particles from the outside of the subjected circuit chip, e.g. from a package of the chip a collide with a capacitor portion of the memory cell, a potential at the capacitor portion is lowered. If such collision of alpha particles with the capacitor portion arises in the aforementioned small-sized memory cell, then since the influence of the alpha particles upon the potential at the capacitor portion is relatively enlarged, a read-out voltage from the memory cell is lowered, resulting in reduction of the voltage difference from a reference voltage, and therefore, correct detection of the stored information becomes difficult. Moreover, transfer of a voltage between a capacitor in a memory cell and a digit line of a memory circuit is effected via a gate transistor in the memory cell, and upon the transfer from the capacitor to the digit line, the voltage at the capacitor is transferred to the digit line after it has been reduced by the amount corresponding to the threshold value of the gate transistor, so that the possibility of occurrence of the abovedescribed malfunction becomes larger. In addition, upon charging the capacitor in the memory cell with a given write-in voltage which is usually provided by power supply voltage, the voltage is applied to the capacitor via the gate transistor in the memory cell, and hence the net write-in voltage has been already lowered by the amount corresponding to the threshold value of the gate transistor. Therefore, the reduction of the read-out voltage level upon reading-out with respect to the write-in voltage level will be still increased.
In order to increase a write-in voltage applied to a memory cell and a read-out voltage therefrom as large as possible, a potential on a selected word line may be raised to a potential higher than a power supply potential level by a bootstrap or the like to make a gate transistor in a memory cell operate in an unsaturated region, to write-in the power supply potential level on a capacitor in the memory cell. However, according to such a method, if the number of memory cells coupled to a respective word line is increased, then a capacitor having a capacitance of several hundreds pico-farads or more is required for the bootstrap, and hence power consumption and the necessary area of the peripheral circuit as well as the bootstrap capacitor become undesirably large. Moreover, the operating speed of such a memory is limited by the operating period of the bootstrap circuit, and consequently, it is impossible to realize a high speed operation.